HARDWARE ROADMAP • CUSTOMER OVERVIEW

QPC Chip: First Usable Model

A roadmap for an expandable QPC-native chip — not a product for purchase today. Current verified evidence runs on IBM / partner QPUs.

This page is the customer overview. To keep a copy, use your browser’s Print or Save as PDF. For formal documents (procurement, legal, partnership), contact your QPC representative.

Target: First Usable Model

The first QPC chip is designed as a usable product with real workloads and a clear path to market-competitive scale.

Scale

32–64 qubit-equivalent (8–16 contextures). Usable for real algorithms: supply chain at reduced scale, benchmarks, research.

Expandability

Modular design: add more contextures and qubits in a second generation. Gen 2 targets 100+ qubit-equivalent (Torino/Pasqal competitive).

Real-World Tasks

Multi-objective optimization, multi-contexture computation, structured problems that benefit from coherent quantum coupling between contexts.

Advantage & Customer Pathway

A focused machine for decisions with several logics at once

The QPC chip is intended for organisations whose decisions cannot be reduced honestly to one score: for example, risk + cost + resilience; carbon + biodiversity + social impact; or premium + risk constraints. It is not positioned as a replacement for every classical optimiser or every general quantum workload.

Target

Teams with a defined multi-logic decision problem, a sponsor, and a clear way to judge whether a result is useful.

How it would be used

The customer supplies agreed business inputs for a bounded task. QPC maps the task, runs the approved computation, and returns an auditable result with the relevant project metrics.

Why native hardware matters

For suitable workloads, native multi-logic coupling can reduce the need to emulate the QPC structure through long general-purpose gate sequences, while keeping the mapping protected and the run repeatable.

Purchase and installation — future route

The QPC Native Chip is a roadmap, not a product available for purchase today. A future customer route would start with a bounded QPC proof on available hardware, followed by a feasibility and procurement review with the chip partner once the first native model is validated.

Initial access: expected to be managed or cloud-hosted access, with QPC and the hardware partner operating the system.
Installation: an on-premise system would require the appropriate cryogenic, control, service, and security infrastructure; it would be planned jointly rather than shipped as a desktop device.
Commercial terms: scope, price, delivery dates, and installation options will be defined only after hardware validation and a partner manufacturing plan exist.

Why This Approach

First model = usable roadmap target, not a sold SKU

A minimal prototype (few contextures, no expansion) would be costly and not usable. A first chip at 100+ qubits in one step would be high risk. The first usable model instead aims to: (i) be realizable with current technology, (ii) run real workloads once fabricated, (iii) be designed from day one for expansion (Gen 2). Until then, QPC evidence is on existing QPUs with public job IDs.

Usability and Speed

Built for real computation

The QPC chip targets multi-contexture workloads: multiple logical contextures evolve in parallel with quantum coupling (transjunctions) between them. End-only readout preserves coherence until the final result. The machine can be fast for workloads that match this architecture; the first model is the step to validate performance and demonstrate advantage where it applies.

Sharing this overview

High-level roadmap and positioning only—suitable for customers and partners reviewing strategy, not implementable design detail.