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Cases solved on gate hardware
Three problems from D-Wave's own public catalogue, re-solved on IBM Heron — the general-purpose quantum hardware D-Wave's headline machine is not.
D-Wave markets itself, across its publications, as a quantum computing company delivering real-world business value. That is true in a narrow and specific sense that the marketing rarely makes explicit: D-Wave's headline systems are quantum annealers. An annealer is a special-purpose device. It searches for the low-energy state of one optimization problem at a time, and it cannot run arbitrary quantum algorithms.
This is not a contested opinion. It is the published consensus, stated plainly in the peer-reviewed literature: D-Wave's quantum annealers are not universal quantum computers and therefore cannot run arbitrary algorithms, being far more limited in their applications because individual qubits cannot be controlled the way a gate-model machine controls them.
Quantum Polycontextural Computing executes on universal gate-model hardware — here, IBM's 156-qubit Heron r2 processor (ibm_fez), the same class of machine that can, in principle, run any quantum algorithm. The question this report answers is direct: take problems D-Wave demonstrates as its commercial strengths, and show that QPC delivers a quantum solution to the very same public instances, on the layer D-Wave's annealer never reaches.
Not a contest of who wins. A demonstration of where each machine stands. The findings below are reproducible from public artefacts and on-record IBM job identifiers.
The contrast needs no embellishment. Set the two architectures side by side, using only what each company publishes about its own systems.
Runs on universal gate-model hardware (IBM Heron r2). Capable, by construction, of arbitrary quantum circuits.
Encodes each problem as a cost Hamiltonian over qubits and finds its ground state through a programmed quantum circuit.
Polycontextural by design: multiple logical contextures coexist within a single 152-qubit execution.
Headline systems are quantum annealers: a specialized model whose sole purpose is optimization, not a universal computer.
Settles a single Ising problem into a low-energy state via analog evolution; cannot run arbitrary algorithms.
Production-scale results route through a classical–quantum hybrid workflow — not a bare quantum processor.
On D-Wave's own pivot. In 2021 D-Wave announced a return to the pursuit of a universal gate-model quantum computer, conceding that fully error-corrected gate-model systems are required for important parts of the quantum application market. After years of presenting annealing as the practical path, the company itself moved toward the universal layer — the layer on which QPC already operates today.
The point is not that D-Wave fails to use quantum physics — it does. The point is what kind of computation results. A full quantum computation, in the strong sense, prepares a coherent quantum state, transforms it through controlled quantum logic, uses superposition, interference and entanglement as computational resources, and measures only once that evolution has built the final probability structure. That is the gate-model logic behind IBM, IonQ, Google and IQM.
A D-Wave annealer does something narrower: it maps an optimization problem into an energy landscape and lets a physical system relax toward a low-energy state. Its computational identity is hybrid by construction — a classical optimization framework wrapped around a quantum-annealing subroutine, with the problem decomposition, constraint handling, embedding and result selection all carried out classically. That is not the same as a coherent quantum algorithm with a quantum-logical transformation and a final measurement.
Said carefully, so it holds. Adiabatic quantum computation can be universal in principle — a proven equivalence to the gate model exists. But D-Wave's machines as actually built are restricted transverse-field Ising annealers, suited to QUBO and Ising optimization, not programmable universal quantum logic. The gap QPC addresses is not "quantum versus not-quantum." It is a restricted special-purpose optimizer versus a universal, programmable quantum machine.
Each case below takes a problem from D-Wave's public demonstration catalogue, builds the identical mathematical instance, and solves it on IBM's universal gate-model processor through QPC. The metric is the energy gap to the known optimum and the validity of the decoded solution. All three returned the optimum exactly.
The cleanest form of parity. D-Wave's demo is a pure QUBO: choose the feature subset that maximises information about the target while minimising redundancy. QPC computes the identical mutual-information coefficients from the same public dataset and solves the same QUBO as a cost Hamiltonian on gate hardware — bit-identical inputs, a different machine.
The selected features — passenger class, sex, title, cabin — are precisely the variables that historically governed Titanic survival. The quantum result is not only optimal in energy; it is correct in substance.
D-Wave's bin-packing demo runs on its classical–quantum hybrid solver and uses continuous position variables — a formulation a bare quantum processor cannot hold directly. QPC takes the same physical instance and solves it by the standard gate-model route: a discretised placement model expressed as a cost Hamiltonian on universal hardware. Same problem, honestly different formulation, fully quantum execution.
Stated plainly: where D-Wave uses continuous variables on a hybrid solver, QPC uses a discretised encoding on a universal quantum processor. The instance is the same; the quantum execution is genuine and complete.
D-Wave's own routing pipeline is two-stage: a quantum-addressed clustering step that assigns clients to vehicles under capacity, followed by a classical routing step. QPC mirrors this structure exactly — and solves the quantum-addressed clustering as a compact 8-qubit cost Hamiltonian on gate hardware, then routes classically, just as D-Wave does. The quantum part runs on the universal layer.
The clustering QUBO was encoded without slack variables, halving the qubit count and giving the gate-model circuit a clean energy landscape — a deliberate engineering choice for universal hardware. The decoded plan splits the four clients into their two natural geographic groups, each vehicle loaded exactly to capacity.
One point must be explicit, because it changes how the results should be read. Every case above was deliberately constrained to a small qubit count and a low number of contextures, matched to what the comparison required for a fair test. This was a choice, not a limit. The instances were sized so their optima are independently knowable and the comparison to D-Wave's problem classes is clean — equal footing, nothing inflated.
QPC's actual operating mode is substantially larger. Its polycontextural architecture runs many contextures concurrently within a single coherent execution — multiple logical problem-contexts evolving together in one quantum run, their amplitudes transformed through interference and entanglement before a single final readout, rather than one problem settled at a time. Combined with the QPC Noise-Reduce application, the working envelope today is bounded only by available hardware — currently 152 of the 156 qubits on IBM Heron r2.
In other words: the parity demonstrated above was achieved while holding QPC to the same modest scale as a single-problem optimizer. The polycontextural design is built to carry far more — more contextures, more qubits, more independent problem-contexts in one run — as hardware permits. The fair-comparison setup understates the architecture by design.
The honest scope: these are demonstration-scale instances, chosen so the optimum is independently knowable and the result is verifiable. That is the point. Parity on public instances, on the universal layer, with nothing hidden — is a stronger position than scale claims that cannot be reproduced.