HSBC FRAUD PILOT · IEEE-CIS PUBLIC DATA · IBM FEZ EXECUTION

QPC PC-QRC-FD: Real-World Fraud Task Pilot

A public fraud-risk pilot: leakage-controlled protocol, classical matched-slice scores, and an IBM Heron r2 run at 156 qubits with archived job IDs.

Reader's guide

Start here for the narrative and metric tables on this page. Follow the chain below for outcomes and job IDs.

  1. This report: executive summary. Task, data contract, simulator / classical / K-ablation, IBM Fez 156-qubit pilot.
  2. Pilot report: workspace paths, reproducibility commands, IBM routing notes, link back to artifacts.
  3. Machine-readable evidence: JSON produced alongside scripts (local partner workspace): HSBC IBM evidence bundle, HSBC tuning bundle, HSBC classical match bundle.
  4. Highlights: short HSBC card with cross-links.

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Task and Goal

The task is HSBC-style fraud detection on card transactions, using public IEEE-CIS Fraud Detection data. QPC’s polycontextural reservoir (PC-QRC-FD) produces fraud-risk features under a leakage-controlled protocol: time-respecting splits and train-only preprocessing fits.

This pilot delivers:

Data Preparation and Computation Contract

Dataset source: Kaggle IEEE-CIS Fraud Detection (`train_transaction.csv` + `train_identity.csv`). Records are sorted by `TransactionDT` to keep chronological structure.

StepProtocol used in this pilot
Time split80% train timeline / 20% test timeline (`time_split_quantile=0.8`)
Pilot train pool1800 rows total = 1500 train-fit + 300 time-ordered validation
Test slice500 rows (stratified subsample on post-cutoff timeline)
Feature selectionMutual information fit on first 1500 train rows only, top 16 numeric columns
Scaling / angle mappingFit on train only; apply to val/test (no fit leakage)
Reservoir readoutPrimarily Z+ZZ expectations with balanced logistic readout

All numbers shown below are pulled from generated artifacts in `Competition 2/Cursor`.

Simulator Architecture Sweep (Main PC-QRC-FD Run)

12q/3c/d6
Best config by test ROC-AUC
0.7435
Best test ROC-AUC
0.1509
Best test PR-AUC
8 seeds
Per architecture screening
ArchitectureTest ROC-AUCTest PR-AUC
8q / 2c / d40.72260.2648
12q / 3c / d60.74350.1509
16q / 4c / d60.71020.2230

Classical References and Matched-Slice Check

ReferenceProtocolROC-AUCPR-AUC
Full classical XGBoost~472k train / 118k test (full split)0.90040.5036
Matched XGBoostSame 1800/500 protocol as quantum slice0.71960.2883
PC-QRC best (12q/3c/d6)Same 1800/500 protocol0.74350.1509

Matched-slice readout: on the same 1800/500 protocol, PC-QRC leads on ROC-AUC (0.7435 vs 0.7196). XGBoost leads on PR-AUC (0.2883 vs 0.1509). Full-split XGBoost (472k / 118k) is in the table as the large-data classical reference.

Polycontexture K-Ablation (Fixed 12 Qubits, Depth 6)

This run keeps total qubits and depth fixed and varies contexture count K. K=1 is a single wide chain; K>1 uses disjoint blocks (polycontextural blocking).

K (contextures)Block sizeTest ROC-AUCTest PR-AUC
1120.73910.2229
260.73450.1858
340.74350.1509
430.72320.1783
620.74560.0919

IBM Hardware Pilot (Heron r2 · ibm_fez, 156 qubits)

Run archived as HSBC IBM evidence bundle. IBM Quantum Platform instance routed as open-instance (open-plan quota). Runtime pinned-name discovery used aggregate listing where needed.

156q/12c
Architecture label (depth 6)
0.7717
IBM capped-test ROC-AUC
0.1750
IBM capped-test PR-AUC
2048
Shots per circuit
48/12/48
Capped train/val/test rows
27
Sampler jobs (12 train + 3 val + 12 test batches)
IBM pilot resultValue
BackendIBM Heron r2 · ibm_fez
Mode[internal mode], readout proprietary readout
Test ROC-AUC0.7717
Test PR-AUC0.1750
Reservoir seed1000
Sample job IDsd7uc5kcinasc738smc80 (train), d7uc6nnmrars73d6puqg (val), d7uc707mrars73d6pv50 (test); full list in JSON (ibm_job_ids_all)
Post-processingProprietary QPC readout aggregation (optional)

IBM Cloud routing used for this archive. The workspace script used open-instance, aggregate fallback where pinning fails, and consistent environment cleanup across short names, CRNs, and Runtime SDK channel ibm_quantum_platform. The 27 Sampler jobs in the table are the hardware record.

Hardware slice: job-backed execution at full logical width on IBM Heron r2, capped train/val/test 48/12/48, 2048 shots per circuit. Simulator tuning used 1800/500. IBM capped-test ROC-AUC 0.7717, PR-AUC 0.1750, with public job IDs in the table.

Data and Source Artifacts

Main data folder used by scripts: Competition 2/data

Numbers in this page come from:

These artifacts are generated in the `Competition 2/Cursor` workspace and should be versioned together with this page when publishing evidence snapshots.

Pilot report ← Home Highlights