Future hardware roadmap · July 2026
QPC Native Chip
QPC is proven today as a logical architecture on existing quantum processors, including IBM Heron r2. The QPC Native Chip is the hardware direction: a processor designed from the beginning for several interacting decision logics in one quantum computation.
Status: QPC computes today on commercial quantum hardware
(IBM Heron r2 · ibm_kingston, ibm_fez, ibm_marrakesh).
The Native Chip is the research, engineering, and partnership roadmap for a
processor built around that same polycontextural architecture.
What would be different?
Most quantum processors expose a general grid of qubits and gates. QPC currently maps its multi-logic computation onto that grid in software. A native QPC machine would make the central structure of QPC part of the hardware architecture: parallel logical arenas, purposeful quantum interaction between them, and a final joint result.
Why explore native hardware?
More direct execution
Native support could reduce the need to emulate multi-logic coupling with long compiled gate sequences on a general-purpose processor.
Automatic, repeatable workloads
A dedicated QPC runtime could execute approved workload families in a consistent, auditable way, rather than rebuilding the full mapping for every run.
Protected architecture IP
Customers could supply business parameters and receive results while the QPC mapping and low-level execution remain protected.
Growth with hardware quality
Better coherence, control, and scale make richer multi-logic computations practical on a dedicated QPC processor.
What problems is it for?
The natural target is a decision problem with several genuine logics that must be considered together: for example risk + cost + resilience, carbon + biodiversity + social impact, or premium + risk constraints. Those are the workloads QPC already runs as co-resident contextures on IBM Heron r2.
Roadmap
Now: evidence on existing hardware
QPC continues to run and test its architecture on available vendor quantum systems, with auditable hardware results and explicit controls.
Next: hardware-partner feasibility
Work with an experienced chip producer to assess a first expandable QPC-oriented hardware model and its control stack.
Later: scaled native systems
Increase the number and richness of parallel logical arenas as device engineering and validated workload results justify expansion.
What exists, and what comes next
- Today: QPC architecture evidence on IBM Heron r2, with public job IDs.
- Next: hardware-partner feasibility for a first expandable QPC-oriented model and its control stack.
- Later: scaled native systems as device engineering and validated workloads justify expansion.
For hardware and strategic partners
QPC is open to discussions with quantum hardware manufacturers, research labs, and strategic partners interested in a processor architecture for coherent multi-logic computation. Detailed device architecture is shared only in the appropriate confidential process.
Discuss the QPC Native Chip →