IBM Heron r2 · 156 qubits · one job · raw counts

Polycontextural
quantum architecture

Several logics sit on the processor together, couple through transjunctions, and return one ranking from that readout. New open-plan desks run on ibm_kingston. The working register is the full 156-qubit Heron r2.

Where QPC sits The layer Hardware returns Evidence Scale Crisis Task Library

Where QPC sits

QPC is the architecture layer on the processors the field already runs. Compilers stay on circuits. QPC runs co-resident logics, one job, one ranking.

Host processors

IBM, Google, Microsoft and the rest of the fleet execute physically quantum machines. Gate-model practice reads that computation as Boolean logic: one Hilbert space, one logic, gates and entanglement.

QPC architecture

QPC is the polycontextural layer on those machines. Many contextures, each with its own logic, hold kenograms and morphograms in superposition and couple through transjunctions. The network compiles to the host. That compilation stays with QPC.

What the sitting returns

Co-resident logics, transjunctional coupling, one job, one readout. Rankings for multi-criteria desks on the processors you already use. QPC sits above gates and circuits. Academic contextuality names the phenomenon. QPC runs it as architecture.

How the layer is built

Four pieces. They compile to the qubits you already use. The host machine stays the host.

Contextures

Each contexture carries its own logic. They are co-resident on the same register. A desk is a named set of those logics, locked before the job runs.

Kenograms and morphograms

Inside a contexture, QPC stores relational pattern. The circuit holds that pattern open until readout.

Transjunctions

Transjunctions couple contextures while the job is live. The joint structure is what we measure: ICC, junction gap, ranking on the coupled arm.

One job, one readout

The decision comes from the quantum counts. Architecture claims stay on raw Sampler data. Resilience sits on the same IBM path as a diagnostic channel. Circuit schedules stay closed.

QPC process: context encoding, polycontextural interaction, transjunction processing, measurement

Context encoding → polycontextural interaction → transjunction → measurement

QPC layer architecture on the host processor

The layer on the host stack. Presentation names map onto the QPC terms below.

Names on the diagram · names in the architecture

Context encodingKenogrammatic and morphogrammatic encoding
Polycontextural spaceCo-resident contextures with morphograms
Interference filteringTransjunctions plus consistency
Context collapseContextural collapse at measurement

What the hardware has returned

Named IBM Heron r2 jobs. Public IDs. Architecture metrics on raw counts. Sixty-two computed QPC cases sit on the home list.

156Q
Heron r2 working width
0.185
ADMET raw junction gap
3 / 3
JSC L5 + MCGS raw pass
27·64·128
PFQM Fez ladder

Mask synthesis · ibm_kingston

ICCAD-2013 on 156 qubits. Six masks, 24 measured contextures, one job. The coupled ranking is the computation. Mask result

ADMET · ibm_marrakesh

Seventeen logics, locked junction RYY. Raw gap 0.185, retention 0.749. Same-day full pass. ADMET desk · Coherent architecture

PFQM · ibm_fez

Three contextures in one circuit: FM, AFM, spin-liquid. Campaign-mean ICC 0.187 at 128Q. PFQM

Joint Structure Challenge · ibm_fez

Coupled versus separable and intracontext controls. L5 3/3 on raw ICC. Architecture discrimination on public jobs. JSC

Real-World Desks Noise Reduction Add-on Estimation vs proof Heron industry pilots

Architecture evidence

QPC is a foundational architecture layer built to sit inside the stacks of quantum hardware makers, cloud platforms, and enterprise quantum teams. The layer is hardware-proven. Integration and acquisition talks open at readytogo@quantumpolycontextural.ai.

IBM Heron flagship

Joint Structure Challenge L5 3/3 raw pass. MCGS July 2026 3/3. Open-instance 13 jobs. Protein 46Q. Aerospace 156Q. Public job IDs on each.

Architecture controls

ICC separability, intracontext controls, coupling ON/OFF ablation. Pre-registered bars cleared on ibm_fez. L6 public dare is open to vendors.

Real-world desks

Cerrado land-use, VW traffic, HSBC fraud pilot, crash detection 128Q Torino, D-Wave catalogue tasks on the gate layer. Published scope on each desk.

Multi-vendor runs

IonQ protein audit, Pasqal, IQM, Azure, Origin Wukong. The same polycontextural encoding on those processors.

Public record

Zenodo preprint June 2026. JSON results on site. Joint Structure Challenge kit. Job IDs a reader can open.

Active frontiers

L6 vendor dare. MCQST outreach. Scaling context count on Heron. Deeper real-data ICC instances.

Heron r2 flagship

  • JSC L5: 3/3 raw ICC pass on ibm_fez
  • MCGS gauge-sector: 3/3 raw pass, July 2026
  • Open-instance orchestration: 13 jobs, 4 to 24 contexts
  • Protein 46Q, aerospace 156Q, coupling ablation
  • Pre-registered controls: separable, intracontext, merge

Fleet and domain

  • IonQ protein folding audit, 8 job IDs
  • IBM Torino 128Q crash-detection run
  • Pasqal, IQM, Azure, Origin Wukong completed
  • Cerrado, VW traffic, HSBC fraud: scoped reports
  • D-Wave catalogue tasks on the universal gate layer

What the site carries

  • Raw IBM counts as the architecture pass
  • Verifiable job IDs and JSON artifacts
  • Zenodo: 10.5281/zenodo.22831221
  • Challenge kit for independent reproduction
  • Resilience labeled as a diagnostic channel

Hardware manufacturers, cloud quantum platforms, and enterprise quantum software companies can open a Design Partner desk or an integration discussion. Write readytogo@quantumpolycontextural.ai or open the Design Partner invitation.

Scale on Heron

The next architecture moves stay on the same metric: raw gaps, locked desks, public jobs.

Active architecture objectives

L6 public dare. Match coupled ICC with separable jobs only. Pre-registered invitation to vendors on the Joint Structure Challenge.

Heron width. Open-instance runs already moved 4 to 24 contexts. Aerospace and Cerrado occupy the full 156-qubit register. Coupling depth stays on production chips.

Physics-motivated instances. MCGS gauge-sector extension passed in July 2026. That template is ready for MCQST and larger sector-split patches.

QPC Chip Analysis QPC Chip · First Usable Model Architecture program
March 2026 · ibm_fez · quality envelope

Boundaries Test Report

A Fez width-and-depth ladder from 16 to 128 qubits. Every published point Exec PASS and Quality PASS on the standard envelope, including compiled depth 1922. A second quality line at 1000 layers marks the IBM depth regime we use for structured readout. Later desks run at 156 qubits.

Open the Boundaries report
Architecture case · ibm_fez

Crisis Task, one ranking

Data-driven Middle East crisis scenarios ran as a QPC desk on IBM Fez. Co-resident logics, one job, one readout. The final ranking and the process sit in the public report.

Open the Crisis Task report

Architecture library

Reports that carry the architecture argument. Open a desk, a hardware proof, or a benchmark.

Desks and programs

Five Real-World DesksIBM evidence, public job IDs Customer Task CatalogFinance, HPC, CO₂, supply, strategy Heron industry pilotsCerrado, traffic, insurance Cerrado compareLand-use portfolio on Heron Holographic memory32Q, partial measure to full pattern RICT encode–decode20Q Fez, graph reconstruction

Hardware proofs

PasqalNeutral-atom analog Origin Wukong72Q superconducting IQM Garnet20Q Resonance Azure QuantumIonQ Forte 35Q IonQ Forte verificationTechnical analysis Harel on IBM65-qubit Torino case

Benchmarks and chip

PQST-64Context-driven sampling, 64Q IBM PQST versus RCS64Q, entropy, HOP, XEB PRCBSRICT CPRP PCRT, 128Q–156Q Comparable benchmarksArchitecture scoreboard E8 lattice test152Q Heron certificate pattern QPC Chip, first usable modelCustomer overview CUDA-Q and QPCEvaluation report QPC and D-WaveCatalogue tasks on the gate layer